1. Field of the Invention
The present invention relates to pixel circuitry for an image sensor and in particular to pixel circuitry for an image sensor having a global shutter mode.
2. Discussion of the Related Art
FIG. 1 illustrates a pixel circuit 100 suitable for operation in a global shutter mode. Circuit 100 comprises a pinned photodiode 102 coupled between ground and a node 104. “Pinned” means that the photodiode is initially at a fixed voltage, such as 0 V, before an accumulation of charge. Node 104 is coupled to a power supply voltage VRT via an overflow transistor 106 controlled by an overflow signal OF, and to a storage node 108 via a transfer gate transistor 110, controlled by a signal TG. Node 108 is further coupled to the supply voltage VRT via a reset transistor 112 controlled by reset signal RST, and to the gate node of a sense transistor 114. Transistor 114 has one of its source/drain nodes coupled to the supply voltage VRT, and its other source/drain node coupled to a pixel line 116 via a read transistor 118 controlled by a signal READ.
Operation of pixel 100 in a global shutter mode will now be described with reference to the timing diagram of FIG. 2.
FIG. 2 shows timing diagrams for signals OF, DATA, TG, READ and RST, applied to the pixels in three adjacent rows in an image sensor n, n+1 and n+2.
Initially, signal OF comprises a pulse and the falling edge of this signal initiates a start of an integration period ti of the pixels in the image sensor. Towards the end of the integration period ti, node 108 of each pixel in the image sensor is reset by applying a short pulse to the gate of reset transistor 112. Next, during a transfer period TR, the signal TG to the transistors 110 of each pixel is asserted high for a short duration, to transfer charge accumulated by a photodiode during the integration period to node 108, and TG is brought low to end the integration period ti.
The signal at node 108 in each pixel in the image sensor is stored until the corresponding row is read. Rows are read consecutively, and in this example the first row to be read is row n. For this, the signal READ applied to pixels in row n is asserted, connecting node 108 to column line 116, and the voltage on line 116 is sampled by sampling circuitry (not shown), as indicated by arrow Ln. Node 108 is then reset by applying RST for a short pulse, and then a reference value is sampled by the sampling circuitry, as indicated by the arrow LREFn. The read pulse then returns low, and the signals captured by the is sampling circuitry at Ln and LREFn are converted into digital format and output as indicated by the DATA signal. Rows n+1 and n+2 are then read one after the other in the same manner.
A problem with the circuit of FIG. 1, and the method described in relation to FIG. 2, is that there is a large delay between the end of the global integration period ti, and the read-out of the last rows that are read during which the image signal stored at node 108 becomes degraded in quality. For example, assuming that the read out of one row of 3000 pixels takes approximately 75 μs, when there are over 2000 rows, the delay before the first row is read may be only 30 μs, whereas the delay before the last row can be 75 ms or more. During this delay, crosstalk between the photodiode and the storage node 108 can add to the signal stored on node 108, and furthermore current leakage from node 108, known as dark current, can cause the signal at node 108 to deteriorate. Such interference is undesirable as it can result in a degrading of the image quality between the first and last pixels to be read.